This invention relates generally to integrated circuit memories, and more particularly to a dynamic random access memory (DRAM) having a variable refresh rate control.
A dynamic random access memory (DRAM) is a well known memory type that depends on a capacitor to store charge representative of two logic states. Generally, each DRAM cell includes a capacitor and an access transistor. The charge stored on the capacitor leaks away over time, requiring the data stored by DRAM cells to be periodically read and rewritten, or xe2x80x9crefreshedxe2x80x9d. The periodic refresh operation requires a significant amount of power.
The amount of charge leakage from the capacitors varies greatly depending on temperature and process variations. A higher temperature causes greater leakage than a relatively lower temperature. Also, process variations can cause greater leakage. Therefore, for DRAMs having a fixed refresh rate, the memory cells must be refreshed at a rate that will guarantee reliable memory retention at worst case leakage. For battery powered devices, it is important for power consumption to be as low as possible. A fixed refresh rate may require higher power consumption than is necessary for reliable operation of the battery powered memory.
Therefore, there is a need for a DRAM having a variable rate refresh control circuit that accurately determines a refresh rate to reliably control the refresh operations of the memory and reduce power consumption of the memory in battery powered applications.